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features ? 0.4 a minimum peak output current ? high speed response: 0.7 s max. propagation delay over temp. range ? ultra high cmr: min. 25 kv/s at v cm = 1.5 kv ? bootstrappable supply current: max. 3 ma ? wide operating temp. range: -40c to 100c ? wide v cc operating range: 10 v to 30 v over temp. range ? available in dip8 (single) and so16 (dual) package ? safety approvals: ul recognized, 3750 vrms for 1 minute. csa approval. iec/en/din en 60747-5-2 approval viorm=891 vpeak applications ? isolated igbt/power mosfet gate drive ? ac and brushless dc motor drives ? inverters for appliances ? industrial inverters ? switch mode power supplies (smps) ? uninterruptable power supplies (ups) truth table led vo off low on high hcpl-314j a 0.1 f bypass capacitor must be connected between pins v cc and v ee . 1 3 shield 2 8 16 14 15 9 n/c cathode anode n/c v cc v ee v o v ee 7 6 10 11 cathode anode v o v cc shield description the hcpl-314j family of devices consists of an al - gaas led optically coupled to an integrated circuit with a power output stage. these optocouplers are ideally suited for driving power igbts and mosfets used in motor control inverter applications. the high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. the voltage and current supplied by this optocou - pler makes it ideally suited for directly driving small or medium power igbts. for igbts with higher ratings the hcpl-3150(0.5a) or hcpl-3120 (2.0a) optocouplers can be used. functional diagram hcpl-314j 0.4 amp output current igbt gate drive optocoupler data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. selection guide package type part number number of channels so16 hcpl-314j 2 lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product
2 package outline drawing hcpl-314j so16 package: ordering information hcpl-314j is ul recognized with 3750 vrms for 1 minute per ul1577. part number option package surface mount tape & reel iec/en/din en 60747-5-2 quantity rohs compliant non rohs compliant hcpl-314j -000e no option so-16 x x 45 per tube -500e #500 x x x 850 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: hcpl-314j-500e to order product of so-16 surface mount package in tape and reel packaging with iec/en/ din en 60747-5-2 safety approval in rohs compliant. example 2: hcpl-314j to order product of so-16 surface mount package in tube packaging with iec/en/din en 60747- 5-2 safety approval and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe. hcpl-314j 8.76 0.20 (0.345 0.008) 7.49 0.10 (0.295 0.004) 10.31 0.18 (0.406 0.007) 3.51 0.13 (0.138 0.005) 0.457 (0.018) 1.27 (0.050) 9 16 15 14 11 10 9 1 2 3 6 7 8 view from pin 16 view from pin 1 0.64 (0.025 min.) 10.36 0.20 (0.408 0.008) 0.23 (0.0091) 8.76 0.20 (0.345 0.008) all leads to be coplanar 0.05 mm (0.002 inches) . dimensions in millimeters and (inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0 - 8 v cc1 v o1 gnd 1 v cc2 v o2 gnd 2 nc v in1 v 1 v in2 v 2 nc 0.10 - 0.30 (0.004 - 0.0118) standoff top view 11.63 (0.458) 2.16 (0.085) 0.64 (0.025) land pattern recommendation
3 regulatory information the hcpl-314j has been approved by the following organizations: iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01. ul approval under ul 1577, compo - nent recognition program up to v iso = 3750 v rms . file e55361. csa approved under csa component acceptance notice #5, file ca 88324. solder refow thermal profle recommended pb-free ir profle 0 time (seconds) temperature (c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160c 140c 150c peak temp. 245c peak temp. 240c peak temp. 230c soldering time 200c preheating tim e 150c, 90 + 30 sec. 2.5c 0.5c/sec. 3c + 1c/C0.5c tight typical loose room temperature preheating rate 3c + 1c/C0.5c/sec. reflow heating rate 2.5c 0.5c/sec. 217 c ramp-d ow n 6 c/sec. max. ramp-u p 3 c/sec . max . 150 - 200 c 260 +0/-5 c t 25 c to pea k 60 to 150 sec. 20-40 sec. time w ithin 5 c of ac tu al peak tempera t ure t p t s prehea t 60 to 180 sec. t l t l t smax t smin 25 t p time tempera ture no tes: the time fr om 25 c to peak tempera ture = 8 minutes max. t smax = 200 c, t smin = 150 c note: non-halide fux should be used. note: non-halide fux should be used.
4 output power C p s , input current C i s 0 0 t s C case temperature C c 200 600 400 25 hcpl-j314 800 50 75 100 200 150 175 p s (mw) 125 100 300 500 700 i s (ma) iec/en/din en 60747-5-2 insulation characteristics description symbol characteristic unit installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 600 v rms i - iv i - iv i - iii climatic classifcation 55/100/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 891 v peak input to output test voltage, method b* v iorm x 1.875=v pr , 100% production test with t m =1 sec, partial discharge < 5 pc v pr 1670 v peak input to output test voltage, method a* v iorm x 1.5=v pr , type and sample test, t m =60 sec, partial discharge < 5 pc v pr 1336 v peak highest allowable overvoltage (transient overvoltage t ini = 10 sec) v iotm 6000 v peak safety-limiting values - maximum values allowed in the event of a failure. case temperature input current** output power** t s i s,input p s, output 175 400 1200 c ma mw insulation resistance at t s , v io = 500 v r s >10 9 ? * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section, iec/ en/din en 60747-5-2, for a detailed description of method a and method b partial discharge test profles. ** refer to the following fgure for dependence of p s and i s on ambient temperature.
5 insulation and safety related specifcations parameter symbol hcpl-314j units conditions minimum external air gap (clearance) l(101) 8.3 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 8.3 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.5 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 100 c average input current i f(avg) 25 ma 1 peak transient input current (<1 s pulse width, 300pps) i f(tran) 1.0 a reverse input voltage v r 5 v high peak output current i oh(peak) 0.6 a 2 low peak output current i ol(peak) 0.6 a 2 supply voltage v cc -v ee -0.5 35 v output voltage v o(peak) -0.5 v cc v output power dissipation p o 260 mw 3 input power dissipation p i 105 mw 4 lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refow temperature profle see package outline drawings section recommended operating conditions parameter symbol min. max. units note power supply v cc -v ee 10 30 v input current (on) i f(on) 8 12 ma input voltage (off) v f(off) -3.6 0.8 v operating temperature t a -40 100 c
6 electrical specifcations (dc) over recommended operating conditions unless otherwise specifed. parameter symbol min. typ. max. units test conditions fig. note high level output current i oh 0.2 a vo = v cc - 4 2 5 0.4 0.5 vo = v cc -10 3 2 low level output current i ol 0.2 0.4 a vo = v ee +2.5 5 5 0.4 0.5 vo = v ee +10 6 2 high level output voltage v oh v cc -4 v cc -1.8 v io = -100 ma 1 6, 7 low level output voltage v ol 0.4 1 v io = 100 ma 4 high level supply current i cch 0.7 3 ma io = 0 ma 7, 8 15 low level supply current i ccl 1.2 3 ma io = 0 ma threshold input current low to high i flh 5 ma io = 0 ma, vo>5 v 9, 15 threshold input voltage high to low v fhl 0.8 v input forward voltage v f 1.2 1.5 1.8 v i f = 10 ma 16 temperature coefcient of input forward voltage ? v f / ? t a -1.2 mv/c input reverse breakdown voltage bv r 3 10 v i r = 100 a input capacitance c in 70 pf f = 1 mhz, v f = 0 v switching specifcations (ac) over recommended operating conditions unless otherwise specifed. parameter symbol min. typ. max. units test conditions fig. note propagation delay time to high output level t plh 0.1 0.2 0.7 s rg = 47 ?, cg = 3 nf, f = 10 khz, duty cycle =50%, i f = 8 ma, v cc = 30 v 10, 11, 12, 13, 14 propagation delay time to low output level t phl 0.1 0.3 0.7 s 14, 17 propagation delay diference between any two parts or channels pdd -0.5 0.5 s 10 rise time t r 50 ns fall time t f 50 ns output high level common mode transient immunity fcm h f 25 35 kv/s t a = 25c, v cm = 1.5 kv 18 11, 12 output low level common mode transient immunity fcm l f 25 35 kv/s 18 11, 13
7 package characteristics for each channel unless otherwise specifed. parameter symbol min. typ. max. units test conditions fig. note input-output momentary withstand voltage v iso 3750 vrms t a =25c, rh<50% for 1 min. 8,9 output-output momentary withstand voltage v o-o 1500 vrms 16 input-output resistance r i-o 10 12 ? v i-o =500 v 9 input-output capacitance c i-o 1.2 pf freq=1 mhz notes: 1. derate linearly above 70c free air temperature at a rate of 0.3 ma/c. 2. maximum pulse width = 10 s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 0.4 a. see application section for additional details on limiting i ol peak. 3. derate linearly above 85c, free air temperature at the rate of 4.0 mw/c. 4. input power dissipation does not require derating. 5. maximum pulse width = 50 s, maximum duty cycle = 0.5%. 6. in this test, v oh is measured with a dc load current. when driving capacitive load v oh will approach v cc as i oh approaches zero amps. 7. maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. in accordance with ul 1577, each hcpl-314j optocoupler is proof tested by applying an insulation test voltage 5000 v rms for 1 second (leakage detection current limit i i-o 5 a). this test is performed before 100% production test for partial discharge (method b) shown in the iec/en/din en 60747-5-2 insulation characteristics table, if applicable. 9. device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. pdd is the diference between t phl and t plh between any two parts or channels under the same test conditions. 11. pins 3 and 4 (hcpl-314j) need to be connected to led common. 12. common mode transient immunity in the high state is the maximum tolerable fdvcm/dtf of the common mode pulse v cm to assure that the output will remain in the high state (i.e. vo > 6.0 v). 13. common mode transient immunity in a low state is the maximum tolerable fdv cm /dtf of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e. vo < 1.0 v). 14. this load condition approximates the gate load of a 1200 v/25 a igbt. 15. for each channel. the power supply current increases when operating frequency and qg of the driven igbt increases. 16. device considered a two terminal device: channel one output side pins shorted together, and channel two output side pins shorted togeth - er.
8 figure 1. v oh vs. temperature. figure 2. i oh vs. temperature. figure 3. v oh vs. i oh . figure 4. v ol vs. temperature. figure 5. i ol vs. temperature. figure 6. v ol vs. i ol . figure 7. i cc vs. temperature. figure 8. i cc vs. v cc . figure 9. i flh vs. temperature. (v oh -v cc ) C high output voltage drop C v -50 -2.5 t a C temperature C c 125 -25 hcpl-j314 fig 01 0 0 2 5 7 5 100 50 -2.0 -1.5 -1.0 -0.5 i oh C output high current C a -50 0.30 t a C temperature C c 125 -25 hcpl-j314 fig 02 0.40 0 2 5 7 5 100 50 0.32 0.34 0.36 0.38 0 -6 i oh C output high current C a 0.6 hcpl-j314 fig 03 0 0.2 0.4 -5 -4 -3 -1 (v oh -v cc ) C output high voltage drop C v -2 v oh v ol C output low voltage C v -50 0.39 t a C temperature C c 125 -25 hcpl-j314 fig 04 0.44 0 2 5 7 5 100 50 0.40 0.41 0.42 0.43 i ol C output low current C a -50 0.440 t a C temperature C c 125 -25 hcpl-j314 fig 05 0.470 0 2 5 7 5 100 50 0.450 0.455 0.460 0.465 0.445 i cc C supply current C ma -50 0 t a C temperature C c 125 -25 hcpl-j314 fig 07 1.4 0 2 5 7 5 100 50 0.4 0.6 0.8 1.2 0.2 1.0 i cc l i cc h i cc C supply current C ma 10 0 v cc C supply voltage C v 30 15 hcpl-j314 fig 08 1.2 20 25 0.4 0.8 0.2 0.6 1.0 i cc l i cc h i flh C low to high current threshold C ma -50 1.5 t a C temperature C c 125 -25 hcpl-j314 fig 09 3.5 0 2 5 7 5 100 50 2.0 2.5 3.0 v ol C output low voltage C v 0 0 i ol C output low current C ma 700 100 hcpl-j314 fig 06 25 400 500 5 20 200 300 600 15 10
9 figure 10. propagation delay vs. v cc . figure 11. propagation delay vs. i f . figure 12. propagation delay vs. temperature. figure 13. propagation delay vs. rg. figure 14. propagation delay vs. cg. figure 15. transfer characteristics. figure 16. input current vs. forward voltage. t p C propagation delay C ns 6 0 i f C forward led current C ma 18 hcpl-j314 fig 11 400 9 15 12 100 200 300 -50 0 t a C temperature C c 125 -25 hcpl-j314 fig 12 500 0 2 5 7 5 100 50 100 200 300 400 t p C propagation delay C ns t plh t phl t p C propagation delay C ns 0 200 rg C series load resistance C 200 hcpl-j314 fig 13 400 50 150 100 250 300 350 t plh t phl v o C output voltage C v 0 -5 i f C forward led current C ma 6 25 15 1 hcpl-j314 fig 15 35 2 3 4 5 5 0 10 20 30 i f C forward current C ma 1.2 0 v f C forward voltage C v 1.8 hcpl-j314 fig 16 25 1.4 1.6 5 10 15 20 t p C propagation delay C ns 0 0 cg C load capacitance C nf 100 hcpl-j314 fig 14 400 20 80 60 100 200 300 t plh t phl 40 t p C propagation delay C ns 10 0 v cc C supply voltage C v 30 hcpl-j314 fig 10 400 15 25 20 100 200 300 t plh t phl
10 figure 17. propagation delay test circuit and waveforms. figure 18. cmr test circuit and waveforms. 0.1 f v cc = 15 to 30 v 47 1 3 i f = 7 to 16 ma v o + C + C 2 4 8 6 7 5 10 khz 50% duty cycle 500 3 nf i f v out t phl t plh t f t r 10% 50% 90% 0.1 f v cc = 30 v 1 3 i f v o + C + C 2 4 8 6 7 5 a + C b v cm = 1500 v 5 v v cm ?t 0 v v o switch at b: i f = 0 ma v o switch at a: i f = 10 ma v ol v oh ?t v cm v t =
11 applications information eliminating negative igbt gate drive to keep the igbt frmly of, the hcpl-314j has a very low maximum v ol specifcation of 1.0 v. minimizing rg and the lead inductance from the hcpl-314j to the igbt gate and emitter (possibly by mounting the hcpl-314j on a small pc board directly above the igbt) can eliminate the need for negative igbt gate drive in many applica - tions as shown in figure 19. care should be taken with such a pc board design to avoid routing the igbt collec - tor or emitter traces close to the hcpl-314j input as this can result in unwanted coupling of transient signals into the input of hcpl-314j and degrade performance. (if the igbt drain must be routed near the hcpl-314j input, then the led should be reverse biased when in the of state, to prevent the transient signals coupled from the igbt drain from turning on the hcpl-314j.) an external clamp diode may be connected between pins 14 & 15 and pins 9 & 10 (as shown in figure 19) for the protec - tion of hcpl-314j in the case of igbts switching induc - tive load. figure 19. recommended led drive and application circuit for hcpl-314j. + hvdc 3-phase ac 0.1 f floating supply v cc = 18 v 1 3 + C 2 16 14 15 270 hcpl-314j +5 v control input rg 74xx open collector gnd 1 7 6 8 10 11 9 - hvdc 0.1 f v cc = 18 v + C rg 270 +5 v control input 74xx open collector gnd 1 v ol
12 figure 20. energy dissipated in the hcpl-314j and for each igbt switching cycle. = 24 v C 5 v 0.6 a = 32 ? rg v cc C v ol i olpeak led drive circuit considerations for ultra high cmr performance without a detector shield, the domi - nant cause of optocoupler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detec - tor ic as shown in figure 21. the hcpl-314j improves cmr perfor - mance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively cou - pled current away from the sensi - tive ic circuitry. however, this shield does not eliminate the capacitive coupling between the led and opt - ocoupler pins 5-8 as shown in figure 22. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocou - pler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or of ) during common mode transients. for example, the recom - mended application circuit (figure 19), can achieve 10 kv/s cmr while minimizing component complexity. techniques to keep the led in the proper state are discussed in the next two sections. selecting the gate resistor (rg) step 1: calculate r g minimum from the i ol peak specifcation. the igbt and rg in figure 24 can be analyzed as a simple rc circuit with a voltage sup - plied by the hcpl-314j. the v ol value of 5 v in the previous equation is the v ol at the peak current of 0.6a. (see figure 6). step 2: check the hcpl-314j power dissipation and increase rg if necessary. the hcpl-314j total power dissipation (p t ) is equal to the sum of the emit - ter power (p e ) and the output power (p o ). p t = p e + p o p e = i f ? v f ? duty cycle p o = p o(bias) + p o ( switching ) = i cc ? v cc + e sw ( r g ,q g) ? f = ( i ccbias + k icc ? q g ? f ) ? v cc + e sw ( r g ,q g) ? f where k icc ? q g ? f is the increase in i cc due to switching and k icc is a con - stant of 0.001 ma/(nc*khz). for the circuit in figure 19 with i f (worst case) = 10 ma, rg = 32 ?, max duty cycle = 80%, qg = 100 nc, f = 20 khz and t amax = 85c: p e = 10 ma ? 1.8 v ? 0.8 = 14 mw p o = (3 ma + (0.001 ma /( nc ? khz )) ? 20 khz ? 100 nc ) ? 24 v + 0.4 j ? 20 khz = 128 mw < 260 mw ( p o ( max ) @ 85 c ) the value of 3 ma for i cc in the previous equation is the max. i cc over entire operating temperature range. since p o for this case is less than p o(max) , rg = 32 ? is alright for the power dissipation. esw C energy per switching cycle C j 0 0 rg C gate resistance C 100 1.5 20 4.0 40 1.0 60 80 3.5 qg = 50 nc qg = 100 nc qg = 200 nc qg = 400 nc 3.0 2.0 0.5 2.5
13 figure 21. optocoupler input to output capacitance model for unshielded optocouplers. figure 22. optocoupler input to output capacitance model for shielded optocouplers. figure 23. equivalent circuit for figure 17 during common mode transient. figure 24. not recommended open collector drive circuit. figure 25. recommended led drive circuit for ultra-high cmr ipm dead time and propagation delay specifcations. hcpl-j314 fig 23 1 3 2 4 8 6 7 5 c ledp c ledn shield c ledo1 c ledo2 hcpl-j314 fig 24 rg 1 3 v sat 2 4 8 6 7 5 + v cm i ledp c ledp c ledn shield * the arrows indicate the directio n of current flow during Cd v cm /dt. +5 v + C v cc = 18 v ? ? ? ? ? ? 0.1 f + C C hcpl-j314 fig 25 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v q1 i ledn hcpl-j314 fig 26 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v hcpl-j314 fig 22 1 3 2 4 8 6 7 5 c ledp c ledn
14 cmr with the led on (cmr h ) a high cmr led drive circuit must keep the led on dur - ing common mode transients. this is achieved by over - driving the led current beyond the input threshold so that it is not pulled below the threshold during a tran - sient. a minimum led current of 8 ma provides ade - quate margin over the maximum i flh of 5 ma to achieve 10 kv/s cmr. cmr with the led of (cmr l ) a high cmr led drive circuit must keep the led of (v f v f(off) ) during common mode transients. for example, during a -dv cm /dt transient in figure 23, the current fowing through c ledp also fows through the r sat and v sat of the logic gate. as long as the low state voltage developed across the logic gate is less than v f(off) the led will remain of and no common mode failure will oc - cur. the open collector drive circuit, shown in figure 24, can not keep the led of during a +dv cm /dt transient, since all the current fowing through c ledn must be supplied by the led, and it is not recommended for applications requiring ultra high cmr 1 performance. the alternative drive circuit which like the recommended application circuit (figure 19), does achieve ultra high cmr perfor - mance by shunting the led in the of state. ipm dead time and propagation delay specifcations the hcpl-314j includes a propagation delay diference (pdd) specifcation intended to help designers minimize dead time in their power inverter designs. dead time is the time high and low side power transistors are of. any overlap in ql and q2 conduction will result in large currents fowing through the power devices from the high-voltage to the low-voltage motor rails. to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn of of led1) so that un - der worst-case conditions, transistor q1 has just turned of when transistor q2 turns on, as shown in figure 26. the amount of delay necessary to achieve this condition is equal to the maximum value of the propagation de - lay diference specifcation, pdd max, which is specifed to be 500 ns over the operating temperature range of -40 to 100c. delaying the led signal by the maximum propaga - tion delay diference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the diference between the maximum and minimum propagation delay difer - ence specifcation as shown in figure 27. the maxi - mum dead time for the hcpl-314j is 1 s (= 0.5 s - (-0.5 s)) over the operating temperature range of - 40c to 100c. note that the propagation delays used to calculate pdd and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical igbts.
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2010 avago technologies. all rights reserved. obsoletes 5989-2943en av02-0169en - february 3, 2010 figure 26. minimum led skew for zero dead time. figure 27. waveforms for dead time. t phl max t plh min pdd* max = (t phl - t plh ) max = t phl max - t plh min *pdd = propagation delay difference note: for pdd calculations the propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on hcpl-j314 fig 27 t plh min maximum dead time (due to optocoupler) = (t phl max - t phl min ) + (t plh max - t plh min ) = (t phl max - t plh min ) C (t phl min - t plh max ) = pdd* max C pdd* min *pdd = propagation delay difference note: for dead time and pdd calculations all propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on hcpl-j314 fig 28 t phl min t phl max t plh max pdd* max (t phl- t plh ) max

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